Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little assist on documentation as well as had a missing file, however I managed to get it to simulate utilizing a free on the internet tool called EDA Playground. This time, I’ll take you with the code details as well as exactly how to run the simulation.
You’ll want to refer to the previous publish if you didn’t checked out it already. The diagrams as well as tables provide a high-level overview that will assist you comprehend the files discussed in this post.
If you wished to really program this on a genuine FPGA, you’d have a little work to do. The memory as well as register initialization is performed in a method that works fine for simulation, however wouldn’t work on a genuine FPGA. Anyway, let’s get started!
File-by-File
If you take each data individually, none of them are extremely difficult to understand. Here’s a quick rundown (I’m utilizing the data names I’ll utilize in my on the internet simulation):
Parameter.v – This is like an include data that sets some fundamental definitions for every other file.
prog.v – This is the direction memory. A simple module, it takes an address as well as presents data for that address. The $readmemb directive reads the data from a data (test.prog).
register.v – The register file. This is almost like the direction memory however it has two checked out ports as well as you can compose to it.
data.v – The RAM memory. This is almost like the registers, however larger as well as with a single checked out port. There is some simulation code that opens a data as well as prints the memory comments, however I deleted that as it was just for debugging. The preliminary content comes from the test.data file.
alu.v – You’d believe this would be complicated, however it isn’t. It just takes two inputs as well as does something to produce the output. Something simple like adds or subtracts. The always @(*) tells Verilog not to produce clocked logic for this. It just turns into some simple gates as well as muxes.
Datapath_Unit.v – This is one of the more complex files, although if you dig into it, you’ll see it is mainly bulk. This data produces all the resources (like the registers as well as memories) as well as wires them together.
Control_Unit.v – one more longer module, this just implements the direction table, setting the control lines based on the present instruction.
ALUControl.v – This data decodes instructions for the ALU. It was missing on the original post. Oddly, there is one more similar CPU on the exact same site that has an ALUControl file, however it is clearly for a different direction set. However, starting keeping that data as well as utilizing the style table, I was able to recreate it. If [fpga4students] corrects this, the files may look extremely different.
design.sv – This data is required for the EDAPlayground simulator I’m using. It contains the top-level elements (the data path as well as the control unit). since EDAPlayground only processes this file, it is necessary for it to include the other files mentioned above. This causes some warnings since each of them has a timescale directive, however this is harmless.
testbench.sv – The testbench isn’t part of the genuine design, however just sets up the simulation as well as collects results. I had to modify it a bit to work with EDAPlayground, however the operation is the same. It just produces a CPU, feeds it a clock, as well as lets it run for a while. The test program as well as memory contents are in test.prog as well as test.data.
Simulation
You can do one of two things. You can open up my copy of the style ready-to-go, however that may not be your finest option. I’d suggest you just go to EDAPlayground and produce a new Verilog project. then begin moving the files over from the original post. You’ll run into errors as well as missing files. See exactly how many you can fix. If you get stumped, then you can utilize my copy to assist you if you get stumped. You’ll discover more that way.
If you do choose to try it, right here are a few tips about EDAPlayground. You don’t requirement UVM/OVM selected, nor do you requirement any type of other libraries. I utilized Icarus Verilog 0.9.7, however you might most likely utilize any type of of the Verilog tools available. You do want to inspect the EPWave checkbox as well as you’ll requirement to add this to the inital part of testbench:
første
begynne
$dumpfile(“dump.vcd”);
$dumpvars;
Use the + indication next to the data name tabs to make new files. EDAPlayground has a limit of ten files per pane. Remember, you’ll have to include any type of .v files you produce in either testbench.sv or design.sv. You don’t requirement to include the data files since the other files utilize them indirectly.
Løpe!
Once you have all the errors worked out, you can press Run as well as you’ll get the waveform viewer, EPWave. You have Å legge til signaler om rate av rate, slik at du kan se CPU på jobb. Det ville være morsomt å legge til noen I / O-enheter i minnet eller noen feilsøkingsporter, slik at du kan se på ting litt bedre. Jeg vil vanligvis se programtelleren, så vel som Registeret komponerer porten for å få et konsept om hva som skjer i innsiden.
Den opprinnelige koden hadde et program som trente mye instruksjoner. Jeg kommenterte det så vel som erstattet det med dette:
0000_0100_0000_0000 // 0000: TONS R0 <- MEM (R2 + 0) Siden R2 = 0 Dette setter 1 i R0 0000_0100_0100_0000 // 0002: Tonn nøyaktig samme i R1 (R1 vil alltid inneholde 1) // sted 8 (byte), 4 (ord): 0010_0000_0101_0000 // 0004: R2 = R0 + R1 0001_0010_1000_0000 // 0006: MEM [R1] = R2 (det er MEM [1] = R2 0000_0010_0000_0000 // 0008: R0 = MEM [R1] 1101_0000_0000_0011 // 000A: Hopp til sted # 4 (CPU vil multiplisere med 2 samt legge til 2) // Ingen retning på 000C, men PC vil henge der mens det behandler hopp Du bør kunne overholde inkrementverdien som komponerer til minnet, samt se på programmet telleren syklus tilbake for å plassere 4 med hver sløyfe. Her er en typisk økt: Jeg forlot en stor del interiør signaler, men du kan se at minneadressen 1 er satt til 2 så vel som deretter til 3 på de aller første to iterasjonene i sløyfen. Slutt spill Er dette en stor akademisk CPU? Jeg er ikke sikker. Noen enklere CPUer eksisterer, men de er ofte lite siden de er vanskelige eller de er ekstremt upraktiske. Alt mer utfordrende enn dette er mest sannsynlig også mye å bite av for en nybegynner. Mens jeg tror du burde ha litt forståelse av grunnleggende verilog før du takler noe som dette, var dokumentasjonen litt sparsom (og forvirrende) i enkelte områder. Tydeligvis var det stor nok siden jeg fikk det til å fungere, men hvis du nettopp har begynt, vil du mest sannsynlig sette pris på litt mer hjelp og forklaringer. Har du en foretrukket akademisk Verilog CPU? Jeg leter fortsatt etter at en person som er "akkurat."